This invention relates, in general, to a method of fabricating an interconnect structure, and more particularly, to a method of reducing capacitance between interconnect lines.
With the constant push towards shrinking the size of semiconductor integrated circuits (ICs), semiconductor device geometries and interconnect lines connecting the semiconductor devices must be reduced. Furthermore, the spacing between interconnect lines must also be reduced to fully achieve smaller semiconductor ICs. However, as the spacing between interconnect lines is reduced to the micron and submicron range, a parasitic intra-level capacitance between the interconnect lines increases. Consequently, it becomes increasingly important to reduce the capacitance between interconnect lines to minimize cross-talk between the interconnect lines and to minimize decreases in semiconductor device speed. In fact, in many cases, the intra-level capacitance of metal interconnect lines has become the limiting factor in determining the speed of many gallium arsenide and silicon ICs.
One approach to reduce the intra-level capacitance increases the spacing between the interconnect lines. However, this proposed solution is not compatible with the original goal of shrinking the size of semiconductor ICs.
A second approach to reduce the intra-level capacitance uses a low dielectric constant material between the interconnect lines, and a third approach deposits a first dielectric layer, etches away the initial dielectric material deposited between the interconnect lines, and refills the etched away portion with a different low dielectric constant polymer. For example, conventionally used CVD oxide has a relative dielectric constant of approximately 4.6, and fluorine doped oxides and organic dielectrics have lower relative dielectric constants of approximately 3.3 and 2.6, respectively.
The second and third proposed solutions produce detrimental side effects and may not sufficiently reduce the intra-level capacitance. With the use of increasingly small spacings between the interconnect lines, the low dielectric constants of many dielectric materials are often not low enough to significantly reduce the parasitic intra-level capacitance. Moreover, the process steps associated with incorporating these dielectrics into a conventional process flow are time consuming, complicated, and expensive. The resulting interconnect structures also may reduce the efficiency of heat dissipation since materials having lower dielectric constants generally have lower thermal conductivity. Furthermore, the resulting interconnect structures create other reliability problems which include, but are not limited to, moisture absorption, adhesion failures, and mechanical stress failures.
Accordingly, a need exists for a method of reducing capacitance between interconnect lines. The method should not be expensive, should not significantly increase the cycle time of the process flow, should not impede thermal dissipation, should not be complicated, and should be compatible with shrinking the size of semiconductor ICs.